This present invention relates to an analog-to-digital converter and more particularly, to a pipelined analog-to-digital converter.
Flash, two-step, interpolating, folding and pipelined are the common types of a high-speed analog-to-digital converter. These types of converters compare input signal with reference signals directly and output digital bits in parallel connection. These types of converters work fast, however the resolution is poor because of superficial measure and power consumption. The limitation of resolution is usually designed from 8 to 10 bits.
The flash converter is the fastest of the above-mentioned high-speed analog-to-digital converters. The resolution would be raised by increasing the amount of comparators in the exponent of 2. The relationship between the amount of comparator N and the resolution B is: N=2Bxe2x88x921. When the resolution is over 8, the number of comparators would be more than 500, and the superficial measure and power consumption of the entire circuit would be very large. Therefore, the resolution of flash converter is limited within 6 to 8 bits.
Because there are too many comparators in a flash converter, other types of high-speed converter are developed. In the types, pipelined analog-to-digital converter has the least elements, so it becomes the main stream in the application of the high-speed analog-to-digital converter.
Please refer to FIG. 1 and FIG. 2. FIG. 1 is the schematic diagram of the pipelined analog-to-digital converter according to the prior art. FIG. 2 is the timing diagram of stage circuit in the pipelined analog-to-digital converter according to the prior art. The pipelined analog-to-digital converter 10 according to the prior art comprises a plurality of stage circuits Sxe2x80x2i (i=1xcx9cn), a register 15 and a digital output code combiner 17. Each stage circuit Sxe2x80x2i according to the prior art comprises a sample and hold operator 12, a comparator 14, an amplifier 16 and a compensator 18. The stage circuit Sxe2x80x2i according to the prior art converts the analog input signal to the digital output signal in two modes: a sampling mode and an amplifying mode.
The operation principle of the pipelined analog-to-digital converter 10 according to the prior art is described as follows. When an external analog signal Vin is inputted into the first stage circuit Sxe2x80x21 of the pipelined analog-to-digital converter 10, the first stage circuit Sxe2x80x21 enters the sampling mode. The sample and hold operator 12 samples the analog signal Vin at sampling time. Moreover, compares sampling signal of the analog signal Vin with a predetermined reference signal Vref of the comparator 14 to generate a digital output code. After that, the stage circuit then enters the amplifying mode. In the amplifying mode, the amplifier 16 amplifies the analog signal Vin. The compensator 18 adds a compensation value to the amplifying analog signal Vin according to the digital output code obtained by comparator 14. After that, the processed analog signal is transmitted to the second circuit Sxe2x80x22.
The following stage circuits repeat the above-mentioned steps. The last stage circuit executes only the sampling mode and compares the analog signal with the reference signal without amplifying. The digital output codes of each stage circuit temporary store in a register 15. When the last stage circuit outputs digital output codes, a digital output code combiner 17 combines the digital output codes to generate the digital signal Bxe2x80x2out corresponding to the analog signal Vin.
Wherein, the resolution K of each stage circuit is based on the number of reference signals in the comparator. If each resolution is 1 bit, the reference signal of the comparator would be xc2x1Vref/4. The amplification factor G of the amplifier in the stage circuit would be confirmed with the confirmation of the resolution. The relationship is G=2K.
Every stage circuit has the sample and hold operator 12 so that they could work at the same time. For example, the second stage circuit simultaneously deals with the analog signal that the first stage circuit inputs into sample and hold operator and transmits the analog signal to the third stage circuit. Therefore, besides the latency at the beginning, the pipelined analog-to-digital converter outputs a result of converting every clock period just as the flash analog to digital converter does.
There are several stage circuits needed in the pipelined analog-to-digital converter that leads to a great number of amplifiers if the resolution of each stage circuit is one bit. 10 bits pipelined analog-to-digital converter needs 9 stages; therefore, 19 comparators and 8 amplifiers are needed. The more amplifiers, the more power consumption. Once the resolution of stage circuits is raised, the power requirement of amplifier and comparator in each stage circuit would be also raised, and it is difficult to lower the power consumption of the entire pipelined analog-to-digital converter. Thus, a new structure of stage circuit that can lower the power consumption of the entire pipelined analog-to-digital converter is needed.
One objective of the present invention is to provide a pipelined analog-to-digital converter for reducing every two stage circuits of the prior art into one stage circuit. The converter of this present invention contains fewer elements and keeps the efficiency. The converter still executes the mission of converting well.
Another objective of the present invention is to provide a pipelined analog-to-digital converter with fewer elements. The power consumption of the converter decreases by reducing the number of the amplifiers.
The present invention provides a pipelined analog-to-digital converter comprising a plurality of stage circuit for receiving an external analog signal, and converting the analog signal via a plurality of pipelined stage circuits to output a digital signal in responsive to the analog signal. Each stage circuit comprises an amplifier, a comparator, a first compensator and a second compensator for converting the inputted analog signal via a sampling mode, a first amplifying mode and a second amplifying mode.
In the sampling mode, the amplifier receives an analog input signal. The comparator compares the analog input signal with a reference signal to generate a first digital output code.
In the first amplifying mode, the first compensator selectively adds a first compensation value to the analog input signal according to the first digital output code, and then generates a first input signal. The amplifier amplifies the first input signal and then generates a first output signal. The comparator compares the first output signal with the reference signal and then generates a second digital output code.
In the second amplifying mode, the first compensator selectively adds a second compensation value to the analog input signal according to the first digital output code and the second digital output code, and then generates a second input signal. The amplifier amplifies the second input signal, and then generates a second output signal. The second compensator selectively chooses a third compensation value according to the first digital output code and the second digital output code. Then the third compensation value is amplified and added to the second output signal to generate an analog output signal that is sent to the next stage circuit.
These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.